HAL –HAL YANG SERING KITA DENGAR BERKAITAN DENGAN MEMORY
The average time interval between a storage peripheral (usually a disk drive or semiconductor memory) receiving a request to read or write a certain location and returning the value read or completing the write
The area of the RAM that stores the bits. The array consists of rows and columns, with a cell at each intersection that can store a bit. The large rectangular section in the center of the die where the memory is stored.
A process in a multitasking system whose execution can proceed independently, “in the background.
A Synchronous DRAM feature that allows the memory chip’s circuitry to close a page automatically at the end of a burst.
Ball Grid Array – a square package with solder balls on the underside for mounting. Use of BGA allows die package size to be reduced by allowing more surface area for attachment. Smaller packaging allows more components to be mounted on a module making greater densities available. The smaller package improves heat dissipation improving performance. See CSP and FBGA.
Basic Input Output System – often referred to as CMOS, the BIOS provides an interface for a computer’s hardware and software. The BIOS configuration determines how your hardware is accessed.
A measure of the capacity of data that can be moved between two points in a given period of time.
Numbering system requiring only two digits: 0 and 1.
Binary Digit – the smallest piece of data (a 1 or a 0) that a computer recognizes.
This is when there is so much memory the chipset needs assistance to deal with the large loading introduced by the large amounts of memory. A buffer isolates the memory from the controller to minimize the load the chipset sees.
A series of 8 bits.
Column-address-strobe. The signal which tells the DRAM to accept the given address as a column-address. Used with RAS and a row-address to select a bit within the DRAM.
CAS Before RAS. Column Address Strobe Before Row Address Strobe. A fast refresh technique in which the DRAM keeps track of the next row it needs to refresh, thus simplifying what a system would have to do to refresh the part.
Complementary High-density Metal Oxide Semiconductor.
Complementary Metal Oxide Semiconductor. A process that uses both N- and P-channel devices in a complimentary fashion to achieve small geometries and low power consumption. On a PC CMOS generally refers to the BIOS information stored on a CMOS chip.
Central Processing Unit. The computer chip primarily responsible for executing instructions.
A small fast memory holding recently accessed data, designed to speed up subsequent access to the same data. Typically used between a processor and main memory.
The number of pulses emitted from a computer’s clock in one second; it determines the rate at which logical or arithmetic gating is performed in a synchronous computer.
Double Data Rate is a type of SDRAM in which data is sent on both the rising and falling edges of clock cycles in a data burst.
Dual Inline Memory Module. A module with signal and power pins on both sides of the board.
Dynamic Random Access Memory. A type of memory component used to store information in a computer system. ‘Dynamic’ means the DRAMs need a constant ‘refresh’ (pulse of current through all of the memory cells) to keep the stored information. (See also RAM and SRAM.)
An individual rectangular pattern on a wafer that contains circuitry to perform a specific function. The internal circuitry is made of thousands of tiny electronic parts. ‘Die’ refers to a semiconductor component or part that has not yet been packaged (also known as ‘IC’ (Integrated Circuit) or ‘chip’).
The physical measurements of the die.
Direct memory access
A computer feature that allows peripheral systems to access the memory for both read and write operations without affecting the state of the computer’s central processor.
Error Correcting Code. Logic designed to correct memory errors.
A feature that allows for faster back to back accesses
Electrically Erasable, Programmable, Read-Only Memory chip. EEPROMs differ from DRAMs in that the memory stays in even if electrical power is lost. Also, the memory can be erased and reprogrammed.
Front Side Bus is the data channel connecting the processor, chipset, DRAM, and AGP socket. FSB is described in terms of its width in bits and it’s speed in MHz.
Joint Electron Device Engineering Council – the group that establishes the industry standards for memory operation, features and packaging.
Level 1 cache. A small cache integrated in processor that provides a small working space for quick access to the most recently used data.
Level 2 cache. L2 cache has the same purpose as L1 cache, but is usually not integrated into the processor. L2 cache is traditionally made of SRAM and in socket 7 and older motherboards was in some cases upgradeable. See COAST.
Megahertz is a measurement of clock cycles in millions of cycles per second.
Millions of Instructions Per Second. This measurement is generally used when describing the speed of computer systems.
Amount of memory equal to 1,048,576 bits of information. (Abbreviated Mb.)
Amount of memory equal to 1,048,576 bits of information. (Abbreviated MB.)
Cache Data SRAM: quick-access chip.
DRAM dynamic random access memory.
SDRAM synchronous dynamic random access memory.
DDR SDRAM double data rate dynamic random access memory.
SLDRAM synchronous link dynamic random access memory.
RDRAM Rambus dynamic random access memory.
EPROM: erasable, programmable, read-only memory.
PROM: programmable, read-only memory.
RAM: random access memory.
ROM: read-only memory (permanent memory that cannot be changed).
SRAM: static random access memory.
Printed Circuit Board; board that contains layers of circuitry that is used to connect components to the outside.
Intel’s PC100 specification defines the requirements for SDRAM used on 100MHz FSB motherboards.
The PC133 specification details the requirements for SDRAM used on 133MHz FSB motherboards. PC133 SDRAM can be used on 100MHz FSB motherboards but will not yield a performance advantage over PC100 memory at 100MHz.
Presence Detect. Indicator pins on SIMMs and DIMMs that provide information to the system using the module.
Pin Grid Array.
Random Access Memory – a data storage device for which the order of access to different locations does not affect the speed of access. Data is typically stored in RAM temporarily for use by the process while the computer is operating.
Row-Address-Strobe: the signal that tells the DRAM to accept the given address as a row-address. Used with CAS and a column-address to select a bit within the DRAM.
Rambus DRAM is an evolutionary type of DRAM that uses a 16-18 bit data path and is designed to operate with FSB speed of 800MHz producing a burst transfer rate of 1.6 gigahertz.
Is a count of the number of rows (in thousands) refreshed at a time in a refresh cycle. Common refresh rates are 1K, 2K, and 4K.
Thin Small Outline Package. It is thinner and slightly smaller than an SOJ and with gullwing-shaped leads. A thin, rectangular package with leads sticking out the sides of the package.
Collector Common Voltage.
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